The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to an interconnect structure having increased reliability and strength of the via to wire connection with no significant impact to resistance or processing complexity.
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate.
As millions and millions of devices and circuits are squeezed on a semiconductor chip, the wiring density and the number of metal levels are both increased generation after generation. In order to provide low RC for high signal speed, low k dielectric materials having a dielectric constant of less than silicon dioxide as well as copper-containing lines are becoming a necessity. The quality of thin metal wirings and studs formed by a conventional damascene process is extremely important to ensure yield and reliability. The major problem encountered in this area today is poor mechanical integrity of deep submicron metal studs embedded in low k dielectric materials, which can cause unsatisfied thermal cycling and stress migration resistance in interconnect structures. This problem becomes more severe when either new metallization approaches or porous low k dielectric materials are used.
To solve this weak mechanical strength issue while employing copper damascene and low k dielectric materials in an interconnect structure, a so called “via punch-through” technique has been adopted by the semiconductor industry. The via punch-through provides a via-gouging feature (or anchoring area) within the interconnect structure. Such a via-gouging feature is reported to achieve a reasonable contact resistance as well as an increased mechanical strength of the contact stud. These findings have been reported, for example, in M. -Si. Liang “Challenges in Cu/Low k Integration”, IEEE Int. Electron Devices Meeting, 313 (2004), D. Edelstein et al. “Comprehensive Reliability Evaluation of a 90 nm CMOS Technology with Cu/PECVD Low k BEOL”, IEEE Int. Reliability Physics Symp., 316 (2004), and U.S. Pat. Nos. 4,184,909 to Chang et al., 5,933,753 to Simon et al., 5,985,762 to Geffken et al., 6,429,519 to Uzoh et al. and 6,784,105 to Yang et al.
However, the argon sputtering technique that is used to create via gouging in the prior art damages the low k dielectric material. Because of the requirement of creating the gouging feature, the final interconnect structure includes severe damage that has been introduced into the low k dielectric material from the Ar sputtering process. This becomes a major yield detractor and a reliability concern for advanced chip manufacturing.
The problem of prior art interconnect structures including via gouging features created by argon sputtering is shown in FIG. 1. Specifically, FIG. 1 shows a prior art interconnect structure including an upper interconnect level 108 located atop a lower interconnect level 100. The lower interconnect level 100 includes a first low k dielectric material 102 which includes at least one conductive feature 104. The at least one conductive feature 104 is typically spaced apart from the first low k dielectric material 102 by a diffusion barrier 103. The conductive feature 104 is typically a metallic line that is embedded with the first low k dielectric material. The lower interconnect level 100 is typically separated in part from the upper interconnect level 108 by a capping layer 106. The upper interconnect level 108 includes a second low k dielectric material 110 that includes conductively filled lines 112 and conductively vias 114 located therein. In some embodiments, as shown in FIG. 1, a conductively filled line 112 is positioned directly above and in contact with a conductively filled via 114. The combination of the conductively filled line 112 and the conductively filled via 114 has a via gouging feature 116 that extends into the at least one conductive feature 104 of the lower interconnect level 100. As is illustrated, the conductively filled lines 112 and the conductively filled vias 114 each include a conductive material. A first diffusion barrier 118 and a second diffusion barrier 120 separate the conductive regions from the dielectric material. Regions 125 shown in FIG. 1 denote the damaged regions that are formed into the dielectric materials during Ar sputtering which is used in creating the via gouging feature 116. The damaged regions 125 result in an undesirable roughness at the bottom of the conductive feature. As is shown on the far right hand side of the drawing, the prior art process also damages the first dielectric layer 102 at a misaligned via pattern 127. A misaligned via pattern is defined when a via is not fully aligned/landed onto the underlying interconnect level.
Both of these characteristics degrade the overall wiring reliability as well as the strength of the via to wire connection. Moreover, both of the aforementioned characteristics result in the structure exhibiting a high-level of metal-to-metal leakage.
Porous ultra-low k dielectric materials (having a dielectric constant of about 2.8 or less) have been developed and have been used in interconnect structures as one of the interlevel dielectrics. As compared to dense (i.e., non-porous) low k dielectrics, the damage impact of argon sputtering is much higher on most ultra-low k dielectric materials tested, which makes integration of the current metallization approach with ultra-low k dielectric materials nearly impossible. As a result, all of the current ultra-low k hardware has failed during barrier integrity testing.
In view of the above drawbacks with prior art interconnect structures, and particularly in those including a porous ultra-low k dielectric as one of the interlevel dielectric materials, there is a continued need for developing a new and improved integration scheme that improves the reliability and strength of the via to wire connection, without introducing any damaged regions into the dielectric material.